A 1/8-rate clock and data recovery architecture for high-speed communication systems

Abstract

A new clock and data recovery (CDR) architecture for high-speed communication applications is introduced. The proposed CDR architecture is described in the context of a 40-Gb/s optical communication system. This architecture utilizes 1/8-rate clock to recover and demultiplex the data, and it does not require a frequency divider. Also, the CDR system employs a rate-reduction block to lower the data transition density and thereby alleviates the speed requirements of the data recovery process. For a 40-Gb/s system, the CDR uses a multiphase voltage-controlled oscillator (VCO) with 5-GHz center frequency. The proposed architecture is particularly suitable for deep submicron CMOS designs where the designer encounters difficulties in implementing a full-rate clock and data recovery.