Abstract
An effective logic synthesis procedure based on the functional decomposition of a Boolean function is presented. A distinctive feature of the proposed method is that the decomposition is carried out as the first step of the synthesis process. The presented procedure is suitable for various implementation styles, including PLAs, PLDs and FPGAs. The results of the benchmark experiments presented show that, in several cases, the method produces circuits of significantly reduced complexity compared to the solutions reported in the literature.
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