Abstract
In the paper new structures for multilayer dynamically reconfigurable transputer systems are presented which enable more efficient reconfiguration of link connections than in the systems so far proposed for the first generation transputers. The proposed structures are based on dynamically on-demand organized interprocessor link connections; synchronous CSP-like interprocess communication model; computational, control and system functions executed in parallel; dynamic loading of processors with subtasks. Multiple transputer-compatible link connection crossbar switches, OCCAM-2 as user parallel programming language and transputer internal code at the system level are used in the proposed architectures.
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