Abstract

The paper presents a new kind of parallel embedded systems implemented in system on chip (SoC) technology, in which inter-processor communication infrastructure is dynamically run-time adjustable to application program requirements. The new system architecture assumes processors with a large number of autonomous communication links, which enables the look-ahead inter-processor connection reconfiguration that overlaps with current program execution including data communication. Dynamic connection reconfiguration pattern is determined at compile-time, as a result of application program graphs analysis. Algorithms for task scheduling and program decomposition into sections executed with the dynamic look-ahead created connections of processor links are presented. Experimental results with structuring of parallel numerical programs of fast Fourier transformation (FFT) are presented. The experiments compare program structuring quality of the look ahead connection reconfiguration in a single crossbar switch but with the use of multiple link subsets intergeably reconfigured in advance with the quality of reconfiguration in a single crossbar switch based on classical on-request approach.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.