Multi Header Based Ultra Low Power MTCMOS Technique to Reduce NBTI Effect in Combinational Circuit

Abstract

With the advancement of technology, negative bias temperature instability (NBTI) emerges out as a major problem for VLSI circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues present extreme unwavering quality issues for CMOS devices. Since both the NBTI and leakage are reliant on input test vector of the circuit however input vector control strategy isn’t viable for bigger circuits. Thus in this paper two design is proposed (1) Single header Based Ultra low Power Diode Tri-mode Technique is designed for reducing leakage and delay of the circuit (2) Multi header Based Ultra low Power Diode Tri mode Technique with Body Bias on all sleep pMOS transistor to mitigate NBTI effect. Experimentations are done on 1 bit full adder circuit with the usage of tanner EDA at 90 nm CMOS technology node and supply voltage 1 V. The results reveal that by using first proposed technique leakage current is reduces by 74.93% and 0.217% respectively as compare to Stacking with delay based MTCMOS method and ULP diode based MTCMOS method. First proposed design is also effective in terms of delay. Result shows that delay get reduced by 20.91% and 7.84% as compare to prevalent techniques. Second Proposed design at 50% Duty cycle is very much effective for NBTI effect mitigation. Experimental result shows that Second Proposed design with reduction in duty cycle(from 100% to 50%) the Vth shift on pMOS transistor reduces and with this decrement in Vth of pMOS transistor NBTI effect on the circuit will get reduced.