Abstract
Crosstalk noise in on-chip interconnect plays a major role in the performance of modern integrated circuits. Multi-aggressor capacitive and inductive coupling complicates both the modeling and mitigation of the noise. A novel method to model and analyze noise in RLC multi-line structures is proposed in this paper, exhibiting an error of up to 9% as compared to SPICE. This method is physically intuitive since it decomposes the noise produced by each of the aggressors into individual capacitive and inductive noise sources. The proposed model and related layout noise mitigation guidelines are applied to crosstalk noise reduction in multi-line structures.
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