Abstract
Magnetic tunnel junction is first integrated into Loop Replica Bit-Line for robust MRAM sensing. The replica bit-line with the replica bit-cells is used to generate sensing enable signal for bit-line delay tracking. As a realization of MTJ device and MRAM circuit interaction, a tunable MTJ-based loop structure with a group of replica cells is applied to control the timing of STT-MRAM, using optimal MTJ resistance at either parallel or anti-parallel state. The logic delay among the discharging groups is compensated for removing its impact on the target timing. The proposed MTJ-LRB structure was implemented with 28-nm CMOS process and 40nm $\times 40$ nm spin-transfer-torque MTJ device, and evaluated in a $512\times 512$ MRAM array. Simulation results show that the sensing latency variation can be reduced by 87.8% and 76.2% compared with the traditional inverter chains and a previous replica BL technique. The proposed MTJ-LRB achieves enhanced timing scheme and process-voltage-temperature tracking ability, which could be applied to future non-volatile memory design.
Published Version
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