Abstract
Feature extraction is an essential part of automatic speech recognition (ASR) to compress raw speech data and enhance features, where conventional implementation methods based on the digital domain have encountered energy consumption and processing speed bottlenecks. Thus, we propose a Mixed-Signal Processing (MSP) architecture to efficiently extract Mel-Frequency Cepstrum Coefficients (MFCC) features. We design MSP-MFCC to pre-process speech signals in the analog domain, which significantly reduces the cost of the analog-to-digital converter (ADC), as well as the computational complexity of the digital back-end. Moreover, MSP-MFCC eliminates the time-consuming Fourier transform in the conventional digital realization by improving processing flow. We fabricated the analog part based on 180nm CMOS mixed-signal technology, then measured the chip. The measured results show the energy consumption of MSP-MFCC is $0.72~\mu \text{J}$ /frame, and the processing speed is up to $45.79~\mu \text{s}$ /frame. MSP-MFCC achieves 95% energy saving and about $6.4\times $ speedup than state of the art. Further, by using the features extracted by MSP-MFCC, speech recognition simulation reaches the accuracy of 98.2%, which also keeps the leading performance to its current counterparts. The proposed MFCC extractor is competitive for integration in the ultra-low-power always-on wearable speech recognition applications.
Highlights
Speech interaction has become an essential way of humanmachine interaction [1], [2], in which, automatic speech recognition (ASR) plays a vital role in perceiving speech signals
CONVENTIONAL Mel-Frequency Cepstrum Coefficients (MFCC) EXTRACTING METHOD The commonly used MFCC extraction process is shown in Fig. 2 [19], including a microphone in the front-end, analog-to-digital converter, and feature extraction in the backend
The measured power consumption of all filters in the different groups speedup than state of the art [4]. This is the best performance ever reported for entire MFCC feature extraction
Summary
Speech interaction has become an essential way of humanmachine interaction [1], [2], in which, automatic speech recognition (ASR) plays a vital role in perceiving speech signals. Some other works [11], [12] about efficient MFCC extraction are proposed based on FPGA for low-cost speech recognition systems. To achieve more energy-efficient and faster feature extraction for wearable automatic speech recognition, a novel mixed-signal processing architecture to extract MFCC features (MSP-MFCC) is proposed here. MSP-MFCC is investigated, improved and implemented from the disciplines of architecture, algorithm, and silicon proven: 1) Architecture Techniques: Proposed mixed-signal processing architecture achieves higher efficiency and faster speed than state of the art. CONVENTIONAL MFCC EXTRACTING METHOD The commonly used MFCC extraction process is shown in Fig. 2 [19], including a microphone in the front-end, analog-to-digital converter, and feature extraction in the backend. The post-processing operations including logarithmic multiplying and Discrete Cosine Transformation (DCT) are performed next to transform the filtered signals to MFCC features.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
