MPPSK数字接收机位同步算法设计与实现

Abstract

本文设计了一种用于MPPSK调制通信系统数字接收机的双窗实时位同步算法。该算法是一种反馈结构位同步算法，由定时误差检测单元、校正器等构成，基于数据辅助来计算定时误差。相较于现有的MPPSK接收机位同步算法，该算法具有同步建立时间短、不依赖冲击幅值、实时调整的优点。最后利用FPGA开发环境System Generator系统设计工具进行设计和仿真，并在基于Spartan-6系列FPGA设计的MPPSK数字接收机上进行了硬件协同仿真和验证。 This pager designs a double windows read-time symbol timing synchronization algorithm for the digital receiver of MPPSK modulation communication system. The algorithm is a feedback structure, which consists of timing error detection unit, corrector unit and so on and the timing error is calculated based on the auxiliary data. Compared with the existing symbol timing synchronization algorithm for MPPSK digital receiver, this algorithm has the advantages of short synchronization setup time, independent of impact amplitude and real-time adjustment. Finally we use the system generator development tools of Xilinx FPGA to do design and simulation, and we do hardware co-simulation and verification on MPPSK digital receiver based on Spartan-6 series FPGA design.