MOSFET based comparator with static reduction logic for SAR ADC in biomedical applications and its comparison with conventional comparator

Abstract

In this paper we have designed and compared MOSFET based conventional comparator (without static power reduction logic) and controlled comparators (with static power reduction logic) for Low Power SAR ADC at 45nm technology. The peculiar advantage obtained after simulating controlled comparator with conventional comparator is power consumption gets reduced by forty four times with almost same propagation delay as of conventional comparator. Both comparators are simulated at 0.6V in 45nm CADENCE Virtuoso technology node. Dynamic power dissipation has come out to be 1.6u and 20u for conventional and controlled comparator respectively. Simulated controlled comparator is suitable for comparison of two signals of the order of 50 MHz frequency range. Minimum voltage difference between two signals to be compared is 0.3 volt for conventional comparator and its value is 0.2 volt for controlled comparator.