An ultra high-resolution low propagation delay time and low power with 1.25GS/s CMOS dynamic latched comparator for high-speed SAR ADCs in 180nm technology

Abstract

In this paper, a new reliable high-resolution and high-speed dynamic latched type comparator with offset cancellation mechanism is presented. The proposed paper presents a 1.25GS/s and achieves 14-bit resolution in presence of 10mV input offset, which means that it is capable of deciding very low voltage differences (even 100μV) at the output nodes, reliably. Also, as simulation results prove that, in the worst-case condition when the Vdd=1V, the propagation delay time of the suggested paper is 292ps, meanwhile, while Vdd=1.8V, the delay time is decreased 126ps, noticeably. The power consumption of the proposed structure is 342 μW with the power supply of 1.8V, as well. To correctness of the proposed comparator performance, Worst-Case input signal and 250 times Monte-Carlo analysis are applied, too, moreover, the active area of the proposed circuit is 18.4∗27μm2. Furthermore, the proposed circuit is the proper candidate for high-speed, high-resolution and low power SAR ADC and other data converter applications. Simulation results of the proposed structure are simulated using the HSPICE BSIM3 model of a standard 0.18μm CMOS process.