Mosaic: A scheme of mapping non-volatile Boolean logic on memristor crossbar

Abstract

Emerging technologies are under research for future VLSI circuits. Memristor crossbar is one of the promising candidates due to its scalability, non-volatility, etc. Non-volatile logic circuits based on memristor crossbar have been proposed recently. However, these logic circuits can merely map a single building block (e.g., 1-bit full adder) on a crossbar, and how to map multiple building blocks on a crossbar is not addressed, which is crucial to implement a VLSI circuit. This paper proposes a scheme to map multiple building blocks on memristor crossbar, which can simultaneously optimize the delay for each block. In addition, two techniques to optimize the design in terms of delay, area and power consumption are proposed. To illustrate the potential of the proposed mapping scheme, multi-bit adders are used as a case study; their delay, area and power costs for both crossbar and its CMOS controller are evaluated. The results show that the optimized designs reduce area (>23%), delay (>26%) and power consumption (>21%) as compared to initial designs. Finally, our designs are compared with state-of-the-art.