MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

Abstract

For applications in the MOS device fabrication the interface properties of sputtered SiO 2 and SiO 2-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO 2 with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated. MOS transistors with sputtered SiO 2 and Si gate material layers and for comparison Al gate devices with sputtered SiO 2 have been fabricated and their threshold voltage behavior was tested.