Abstract
Continued scaling of the interconnect geometry increases the metal resistance which degrades the performance of SRAM in advanced technology nodes. We propose an energy-efficient multi-tiers monolithic 3D (M3D) SRAM cell design with stacked 2D material nanosheet FETs to release the impact of metal line resistance. Considering the 2nm node design rules, the 3-tier M3D SRAM cell with stacked MoS2 FETs shows a 42% reduction in cell area, 49% improvement in read access time, and 68% improvement in energy-delay product. The energy- and area-efficient high-performance 3- tier M3D SRAM cell enables intelligent functionalities for the area and energy-constrained edge computing devices.
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