Monolithic 3D Compute-in-Memory Accelerator with BEOL Transistor based Reconfigurable Interconnect

Abstract

CIM-based inference engine with FeFET is projected to exhibit excellent energy efficiency, but its area scaling is still limited by availability of logic voltage compatible FeFET at leading-edge node. This work performs system-technology co-design (STCO) of a monolithic 3D (M3D) CIM accelerator using back-end-of-line (BEOL) compatible oxide channel MOSFET and FeFET, where Wdoped In2O3 (IWO) NMOS is utilized to design area-efficient M3D write circuit and the IWO-based FeFET is adopted as the routing switch for reconfigurable interconnect. From a system-level evaluation, our M3D IWO FeFET design (utilizing a hybrid 22nm/7nm M3D partition) shows 2.9× times higher energy efficiency than a 7nm SRAM design with comparable chip area. The chip area can be further reduced by improving the electron mobility of the oxide channel.