Abstract
For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA) compared to the conventional M3D SRAM (SRAM3D). SRAM3D could not directly connect the top-tier device and the bottom-tier metal line. Thus two tiers had to be connected by bypassing the metal line. As a result, SRAM3D wasted the area to place the monolithic interlayer via and did not get 50 % area scaling. However, gate and S/D bottom contact schemes, GBC and SDBC, could solve these problems. Although these methods required additional process steps, they brought significant advantages in interconnect RC and PPA. Based on a 26 nm width nanosheet transistor, SRAM3D showed a 30 % area reduction compared to 2D SRAM (SRAM2D), whereas SRAMSDGBC showed a 50 % area reduction. In the ideal (worst) case which ignoring (considering) the array resistance, the read and write access time of SRAMSDGBC were improved 7.7 % (19 %) and 8.3 % (33 %) than SRAM3D, and the write dynamic power was improved by 5.9 % (5 %). Especially, SRAMSDGBC showed improved PPA in the worst case compared to SRAM2D_Cu, which had relatively small interconnect resistivity. Namely, GBC and SDBC schemes are essential to enhance the PPA of M3D cells and will be a promising scheme in M3D SRAM and other logic cells.
Highlights
Si fin-shaped transistor (FINFET) and nanosheet transistor (NSFET) have been scaled down to 3-nm node and leading the semiconductor industry [1]
For GBCTop and SDBCTop, Ieff were almost the same as ConvTop because of similar no stress condition, and there was no significant change in the device itself
SRAMGBC had reduced CBL and CWL compared to SRAM3D because it had a small cell width and a small length of metal line 2 (M2) lines
Summary
Si fin-shaped transistor (FINFET) and nanosheet transistor (NSFET) have been scaled down to 3-nm node and leading the semiconductor industry [1]. It is difficult to scale the contact-poly-pitch (CPP) to less than 42 nm [2] due to the device performance degradation by the short channel effect despite having excellent gate controllability Various studies such as source/drain patterning (SDP), buried power rail (BPR), complementary FET (CFET), and monolithic 3D (M3D), which can reduce the cell area in. When devices need to be compactly integrated like static random access memory (SRAM) array, additional space consumption for MIV reduces the advantage of M3D. To solve this problem, new contact schemes which directly connect the bottom-tier metal line and the top-tier. For a more accurate and comprehensive analysis of the SRAM array, the degradation of the top device and diverse array resistance conditions was considered
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