Modular construction of model partitioning processes for parallel logic simulation

Abstract

Logic simulation of complex VLSI models is very time consuming. Simulation speed can be increased by model partitioning and assigning the resulting parts to simulator instances which cooperate over a loosely coupled system. We have developed a distributed framework, parallelMAP, that implements a hierarchical model partitioning strategy. It can serve both as production environment in VLSI design and as an experimental test bed for algorithm development. In this paper, we describe the possibilities that parallelMAP offers for the modular construction of partitioning processes, starting from basic sequential and parallel modules. Experimental experiences refer to IBM processor models comprising from 1.5 x 105 to 2.5 x 106 elements at gate level.