Modified logical FPGA element

Abstract

Logic elements of programmable logic integrated circuits type FPGA (field-programmable gate array), the so-called LUT (Look Up Table), calculate one logic function from generally not more than 4 variables. This limitation of Mead and Conway is connected with the length of transmission transistors chain. However, by decomposition one constructs LUT with 5, 6 and even more variables. Nevertheless, only one logic function, customizable by the user by downloading the configuration memory SRAM is calculated. At the same time during the process of computation only half of the tree transistors is always activated. This makes the conditions for the use of second half calculation of her second function with the introduction of another pair of the leading variable. But this requires to connect SRAM configuration memory, which stores the settings of the second function. The corresponding truth table is stored overturned compared to the «truth» table of the first function. The second pair of transistors enables the issuance of the senior variable values of the second function. The article discusses the complexity of the assessment of the proposed DubleLUT compared with the realization of two functions in two different LUTs. The conclusion is about the success in the complexity by 10% without taking into account the complexity of switching variables which increase this gain. It is estimated as a gain in the realization of functions with more than 4 variables.