Modes of Operation and Optimum Design for Application of Source-Gated Transistors

Abstract

We show that the source-gated transistor has two distinct modes of operation. In the low-field mode, the current from the reverse-biased source barrier is restricted by the depleted semiconductor at the drain end of the source. In the high-field mode, the current depends on field-dependent barrier lowering in the same region of the source. In practice, both these modes usually occur: the former at low VG, the latter at high VG. It is shown that this understanding enables us to design devices in which the current is insensitive to large changes in structure and geometry.