Modelling of trap assisted tunnelling through thin dielectric layers

Abstract

A detailed model is proposed of the leakage current due to tunnelling through defect traps in thin insulating layers. Such leakage currents are a major concern for the reliability of semiconductor devices based on the insulating properties of dielectric layers, such as metal-oxide-semiconductor transistors and memories, and of nanoscale devices whose operation is based on controlled tunnelling through thin dielectrics. The proposed model allows the addressing of both dc and noise properties of trap assisted currents. Results from a numerical implementation of the model are also presented.