Modelling of single, coupled, L and T type interconnects using state space approach

Abstract

In this paper, we propose models for single, coupled, L and T type on-chip global interconnect lines. Generalised models for different interconnect geometries are formed by distributed RLGC parameters using state space approach. Interconnect delay for a single interconnect line is estimated using our model and compared with other models. It is found that the error in the estimation of the delay is less in our model. Also interconnect performance metrics for the proposed models are obtained for 65 nm, 90 nm, 130nm and 180nm technology nodes based on Predictive Technology Model (PTM) values. In case of coupled, L and T section interconnects, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and can be used to characterise any interconnect structure. Further, the state matrices for any length of interconnect can be obtained by considering suitable number of rlgc segments.