Effect of Mutual Inductance and Coupling Capacitance on Propagation Delay and Peak Overshoot in Dynamically Switching Inputs

Abstract

The shrinking feature size of MOSFET devices is largely responsible for growth of VLSI circuits. In DSM technology below 0.18 μm, interconnect parasitics are significant and erupt as performance limiting parameters of the circuit. Because of short spacing between interconnects, faster signal rise time, longer wire length and use of low K-dielectric material, the coupling capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) and mutual inductance (M) are introduced among on-chip interconnects. This paper presents in-depth analysis of the effects of coupling parasitics on wire propagation delay and peak overshoot voltage for both in phase and opposite phase switching of inputs. To support our analysis, two distributed RLC interconnects coupled inductively and capacitively are taken into consideration. For capturing the effects of coupling parasitics, interconnects are simulated and SPICE waveforms are generated at far end of transmission line. It is illustrated that inductive and capacitive couplings have conflicting effects on wire propagation delay. However, the effect on peak overshoot voltage is of different kind.