Modelling of Parallel Unsigned 2n-1 Modular Arithmetic Multiplier for RNS

Abstract

Modular Multiplication operations are widely used in Digital crypto processors. Modulo multipliers is an essential block for Residue Number System (RNS) computation. Pointing to increase the performance of the RNS computation, the parallel unsigned modulo multiplier for 2n-1 moduli is designed. A mathematical modelling, VLSI architecture and real-time verification are done in this work. Further, the modulo multipliers are described usingVerilog HDL, and the synthesize results for both FPGA and ASIC technologies are presented. Comparison is made based on the parameters such as Area, Power, Delay, PDP& ADP using Cadence RTL Compiler with 180 nm, 90 nm and 45 nm TSMC CMOS Technologies.From the analysis indicate that the proposed multiplier provides a 16% area reduction and 40% speed improvement with a better PDP and ADP performance compared tothe existing modulo multipliers. Finally, the usefulness of 2n-1 modulo multiplier in RNS environment is discussed.