Modelling circuit delays in a demand driven simulator

Abstract

Logic-level simulation of a digital circuit is commonly effected using a discrete event-driven strategy. We have, alternatively, employed a demand-driven simulation strategy in which simulation speed is improved by avoiding unnecessary component activations and signal evaluations. In this paper we describe the application of this method to the simulation of both logic and timing behaviour. Preliminary results are presented, showing significant performance gains in comparison with event-driven simulation.