Modelling and Simulation of 16-bit Vedic Multiplication Using FPGA

Abstract

As India is becoming digital India, so focusing towards digitization, there is requirement of updating the capacity of the processors becomes essential. Arithmetic is the basic component of any processors, multiplication is one of the principal procedure utilized in a number-crunching activities. To design the multiplication module require more hardware resources in contrast with addition & subtraction module. Therefore the present paper deals with study of multiplier to be operated using low power, less area & complexity and execution done with high speed in less time. Hence the implementation of the multiplier with above all requirements through Vedic Science. Vedic mathematics is primordial method of mathematics, which uses the exclusive techniques founded on sixteen sutras. The proposed paper focused on urdhva tirvakbhyam sutra, which is one of the method in Vedic mathematics dedicated for multiplication as it can be solved easily using vertical and crosswise manner. According, it diminishes the time, power, speed and in terms of area also. This paper discusses the 16-bit Vedic multiplication using verilog coding and simulation mode via software..