Abstract
We introduced a novel water-gated field effect transistor (WG-FET) which uses 16-nm-thick mono-Si film as active layer. WG-FET devices use electrical double layer (EDL) as gate insulator and operate under 1 V without causing any electrochemical reactions. Performance parameters based on voltage distribution on EDL are extracted and current-voltage relations are modelled. Both probe- and planar-gate WG-FETs with insulated and uninsulated source-drain electrodes are simulated, fabricated and tested. Best on/off ratios are measured for probe-gate devices as 23,000 A/A and 85,000 A/A with insulated and uninsulated source-drain electrodes, respectively. Planar-gate devices with source-drain insulation had inferior on/off ratio of 1,100 A/A with 600 μm gate distance and it decreased to 45 A/A when gate distance is increased to 3000 μm. Without source-drain electrode insulation, proper transistor operation is not obtained with planar-gate devices. All measurement results were in agreement with theoretical models. WG-FET is a promising device platform for microfluidic applications where sensors and read-out circuits can be integrated at transistor level.
Highlights
In this paper, we present the realization and modelling of a water-gated field effect transistor (WG-FET) which uses 16-nm-thick mono-Si film as channel layer
Working principle of WG-FET device is summarized for probe- and planar-gate topologies in Fig. 1b,c, respectively
To verify the Vg_EDL (x) function and extract parameters, electric field and voltage distribution simulations of WG-FET devices with probe- and planar-gate setups are performed with COMSOL
Summary
We present the realization and modelling of a water-gated field effect transistor (WG-FET) which uses 16-nm-thick mono-Si film as channel layer. It combines the advantages of planar electrolyte-gated OFET design with the high performance of single crystalline Si layer. Fluidic interfaces of these devices provide an integration platform for sensors and their read-out circuits at transistor level. Positive charge carriers are attracted to the interface surface in Si layer with application of negative VGS to the gate electrode.
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