Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits

Abstract

Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are efficient for the design of analogue CMOS circuits are discussed and validated. These analogue models are then used to investigate the significant performance improvement that several basic analogue cells can achieve when optimized in fully depleted SOI CMOS, rather than in bulk CMOS technology. Experimental verifications support this original demonstration of the great potential of fully depleted SOI CMOS for low voltage, low power analogue applications.