Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models

Abstract

A method of modeling CMOS logic circuits for an accurate prediction of timing and logic operations is presented. In this methodology the “lego” concept is used for modeling logic gates and interconnection delays. The model contains complete timing properties integrated with logic operations. These timing properties are used to adjust the timing behavior of a logic circuit in simulation. An important application of this modeling method is in a synthesis process where lego timing models can be assembled as their corresponding hardware blocks are being placed and routed. All input and output values are represented in a discrete 10-region responsive logic value system. The models react to input values that cross the boundary of a region. This modeling method is implemented in VHDL.