Modeling the Thermal-Compression Flip-Chip Process by Finite Element Analysis

Abstract

Abstract For the first time, finite element analysis (FEA) is applied to the thermal-compression flip-chip process in micro-electronics. By adding the bump height nonuniformity and the morphology variance, a common basal line is established. Although the experiment confirms the rate dependence of indium, an approximation is made to derive the material properties in FEA. The relative standard deviation (RSD) of deformation between the FEA model and the reality is around 1% when predicting the misaligned flip-chip specimen. Besides, the modeled bump characteristic with misalignment coincides with the cross-sectional scanning electron microscope (SEM) picture. The model could be served as a powerful tool to guide the manufacturing process.