Modeling the Power Variability of Core Speed Scaling on Homogeneous Multicore Systems

Zhihui Du,Victor W Lee,Ligang He,Richard Vuduc,David A Bader,Rong Ge

doi:10.1155/2017/8686971

Abstract

We describe a family of power models that can capture the nonuniform power effects of speed scaling among homogeneous cores on multicore processors. These models depart from traditional ones, which assume that individual cores contribute to power consumption as independent entities. In our approach, we remove this independence assumption and employ statistical variables of core speed (average speed and the dispersion of the core speeds) to capture the comprehensive heterogeneous impact of subtle interactions among the underlying hardware. We systematically explore the model family, deriving basic and refined models that give progressively better fits, and analyze them in detail. The proposed methodology provides an easy way to build power models to reflect the realistic workings of current multicore processors more accurately. Moreover, unlike the existing lower-level power models that require knowledge of microarchitectural details of the CPU cores and the last level cache to capture core interdependency, ours are easier to use and scalable to emerging and future multicore architectures with more cores. These attributes make the models particularly useful to system users or algorithm designers who need a quick way to estimate power consumption. We evaluate the family of models on contemporary x86 multicore processors using the SPEC2006 benchmarks. Our best model yields an average predicted error as low as 5%.

Highlights

We consider the problem of how to model the power of a modern multicore processor as a function of the speed of its cores
Our models are at the system level and eliminate the need to model individual architectural components with hardware performance events. We explore this family of models systematically, to show how one can “derive” a suitable power model for multicore processors by experiments
We carry out the experiments using SPEC2006 [13] on contemporary multicore processors and obtain a “basic power model” with an average relative error of 3% for most benchmarks. These results help bolster the practical case for using our approach. For those applications in which the basic power model is not as accurate, we find that an improved piecewise model, which partitions the maximum frequency among the cores into a small number of segments, best expresses overall power consumption of a multicore processor

Summary

Introduction

We consider the problem of how to model the power of a modern multicore processor as a function of the speed of its cores. In the classic single-core model, the power, PSC, consumed by a core is expressed as the following function of its operating frequency (“speed”), f: PSC (f) ∝ α ⋅ fβ, (1). (1) omits a term for constant (or static) power, but our argument and methods hold with or without the term. This model appears in a variety of papers on the power-aware scheduling problem [1, 2], in particular when the system provides dynamic voltage and frequency scaling (DVFS) [3, 4]

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