Modeling the instability behavior of thin film devices: Fermi Level Pinning

Abstract

We investigate the underlying physics of degradation/recovery of a metal/n-CdTe Schottcky junction under reverse or forward bias stressing conditions. We used Sah-Noyce-Shockley (SNS) theory to investigate if the swept of Fermi level pinning at different levels (under forward/reverse bias) is the origin of change in current-voltage characteristics of the device. This theory is based on Shockley-Read-Hall recombination within the depletion width and takes into account the interface defect levels. Fermi Level Pinning theory was primarily introduced by Ponpon and developed to thin film solar cells by Dharmadasa's group in Sheffield University-UK. The theory suggests that Fermi level pinning at multiple levels occurs due to high concentration of electron-traps or acceptor-like defects at the interface of a Schottky or pn junction and this re-arranges the recombination rate and charage collection. Shift of these levels under stress conditions determines the change in current-voltage characteristics of the cell. This theory was suggested for several device such as metal/n-CdTe, CdS/CdTe, CIGS/CdS or even GaAs solar cells without a modeling approach to clearly explain it's physics. We have applied the strong SNS modeling approach to shed light on Fermi Level Pinning theory. The modeling confirms that change in position of Fermi Level and it's pining in a lower level close to Valence band increases the recombination and reduces the open-circuit voltage. In contrast, Fermi Level pinning close to conduction band strengthens the electric field at the junction which amplifies the carrier collection and boosts the open-circuit voltage. This theory can well explain the stress effect on device characteristics of various solar cells or Schottky junctions by simply finding the right Fermi level pinning position at every specific stress condition.