Modeling the Failure Mechanism of Electrical Vias Manufactured in Thick-Film Technology

Abstract

Hybrid-thick-film circuits consist of many different components, like screen-printed passive elements (conductors, resistors, and electrical vias), SMDs, and active elements like transistors or ICs. Whereas most of passive components are well investigated and described, the electrical vias often remain unattended. Resistive heating caused by high current pulses might lead to the destruction of the vias. In previous work, we set up a 3d FEM model and investigated the influence of non-radial-symmetric contacting and geometric irregularities of the vias on the occurring maximum temperatures. The present contribution deals with the modeling of a failure mechanism of an electrical via caused by high current pulses. When the local temperature exceeds a defined melting temperature, the metallization layer melts and is not available for conduction any more. The current density rises as a consequence of the decreased cross section area of the vias and leads to a higher heat production in a smaller area. This conducts further melting of the metallization layer and results in a positive feedback that accelerates the destruction of the via. The approach of this contribution is to model the described failure mechanism in a 2d-radial-symmetric FEM model. The modeling results were validated using high current measurements of electrical vias. Modeling and measurement of the voltage drop during a constant current pulse agree very well, from very low current density pulses up to pulses that lead to the destruction of the vias.