Modeling the critical area in yield forecasts

Abstract

Semiconductor device yield is determined primarily by the defect density and the critical area, i.e., that portion of the circuit active area in which the occurrence of a defect results in yield loss. A mathematical theory is developed for fault probability and critical area in terms of device geometry and defect size distribution. Equations are derived for its computation for different geometries, and the physical significance of the parameters contained in the equations is discussed.