Abstract

For modern processes at 90-nm and 65-nm technology nodes, the random yield loss can contribute much to the total yield loss. Hence, it is essential to calculate the critical area to analyze the areas of design, and make changes to improve random yield. The paper provides a novel weighted critical area (WCA) of arbitrary defect outline, which takes the clustering effect in the metal and empty regions of the chip as well as the size distribution of random defects into account. The proposed WCA can serve as a proxy for the random yield loss, and can provide the reliable foundations for a flag area of design for designer to guarantee a reduction of the yield loss.

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