Modeling of Stacking Faults in 4H-SiC n-Type Epilayer for TCAD Simulation

Abstract

Current–voltage characteristics of an n-type 4H-silicon carbide (SiC) epilayer containing a stacking fault (SF) were analyzed using a technology computer-aided design (TCAD) simulation. In the simulation, the SF was modeled by a quantum well (QW) formed in the conduction band, which traps electrons and induces a potential barrier. The simulation analysis clarified that the electron conductance in the n-type epilayer containing a SF was dominantly determined by the potential barrier height. Based on this insight and the experimental results obtained from our previous study, the energetic depth and width of the QW in the conduction band were deduced for four types of SFs. The temperature dependence of the experimental current–voltage characteristics of Schottky barrier diodes (SBDs), containing the SF, was effectively reproduced by adopting the deduced QW depth and width, proving the feasibility of the proposed simulation model quantitatively predicting the impacts of SFs on SiC unipolar device performances.