MODELING OF SILICON WAFER VIBRATION IN SEMICONDUCTOR PROCESS TOOLS

Abstract

An investigation of the behavior of bare, unprocessed silicon wafers during their loading and transport in wafer cassettes is documented. Semiconductor process tools can generate sufficient vibration to cause the current 200-mm diameter wafers to vibrate inside the cassettes leading to particle generation, mechanical misalignment, and wafer walking. The cassettes feature chamfered slots into which the wafers are inserted. In the interest of minimizing particle generation in the cleanroom environment, the wafers slide loosely into the slots. As a result, the wafers show distinct pitching and rattling behavior under certain excitation conditions. A study of the wafer dynamics, when positioned in the cassette slots, shows that the wafers make a transition to instability under repeatable conditions of excitation frequency and amplitude. The development of two models of the wafer behavior is included, as well as an experimental verification of the model's results for 200-mm wafers. The model is expected to predict the behavior of future wafer sizes including the 300-mm wafers now under development.