Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures

Antonio Cerdeira,Marcelo A Pavanello,Magali Estrada,Genaro Mariniello Da Silva,Jaime Calcade Rodrigues

doi:10.1109/laedc54796.2022.9908193

Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures

Antonio Cerdeira, Marcelo A Pavanello + Show 3 more

https://doi.org/10.1109/laedc54796.2022.9908193

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Publication Date: Jul 4, 2022

Affiliation: Center for Research and Advanced Studies of the National Polytechnic Institute, Centro Universitário da FEI

#Nanosheet Transistors #Nanowire Transistors + Show 5 more

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Abstract

In this work, we demonstrate that the Symmetric Doped Double-Gate Model (SDDGM), previously validated for modeling FinFETs, stacked nanowire, and nanosheet transistors at room temperature, can be extended for modeling stacked nanowire and nanosheet transistors at high temperatures. The modeled results are validated by comparison with experimental data.

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