Abstract
This paper describes the effect of geometry in charge-trap (CT) memory devices. We first theoretically analyze the impact of the curvature radius on the behavior of the gate current in Gate-All-Around devices, and then describe the change to make to planar model in order to fit the cylindrical devices characteristics. This model is used to simulate Nanocrystal and SONOS program, erase and retention behaviors. The dynamics enhancement during program/erase due to the bending of the active region in such cylindrical devices is explained. The scaling perspectives conclude this paper.
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