Modeling of high-current source-gated transistors in amorphous silicon

Abstract

Compared with the field-effect transistor, the source-gated transistor has a much lower saturation voltage and higher output impedance. These features are investigated using computer modeling for amorphous silicon transistors operated at high currents when source barriers are low. In particular, it is shown that low saturation voltages are maintained at high current and are insensitive to source-drain separation. Furthermore, the output impedance is preserved even for submicron source-drain separations.