Modeling of HCD Kinetics for Full ${V}_{{G}}$ /${V}_{{D}}$ Span in the Presence of NBTI, Electron Trapping, and Self Heating in RMG SiGe p-FinFETs

Abstract

A SPICE compatible compact modeling framework is proposed for the time kinetics of threshold voltage shift ( $\Delta {V}_{T}$ ) in FinFETs subjected to hot carrier degradation (HCD) stress. The model is valid for the entire drain ( ${V}_{D}$ ) and gate ( ${V}_{G}$ ) voltage space and calculates the generation of interface traps for pure HCD ( $\Delta {V}_{\text {IT-HC}}$ ) and for negative bias temperature instability (NBTI) ( $\Delta {V}_{\text {IT-BT}}$ ), hole trapping ( $\Delta {V}_{\text {HT}}$ ), and electron trapping ( $\Delta {V}_{\text {ET}}$ ) as necessary, and considers the self-heating effect (SHE). The model is validated by using ultrafast (10- $\mu \text{s}$ delay) measured data from replacement metal gate (RMG) silicon germanium (SiGe) p-FinFETs having a different fin length (FL) and different nitrogen (N%) in the gate insulator stack. A calibrated TCAD framework is used to verify the impact of pure NBTI for varying ${V}_{G}$ and ${V}_{D}$ stress in the presence of SHE but no HCD.