Modeling of Grain Boundary Barrier Height for Undoped Polycrystalline Silicon Channel in Macaroni MOSFETs

Abstract

In this article, a physically based explicit analytical model for grain boundary (GB) barrier height ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {B}}$ </tex-math></inline-formula> ) near the polycrystalline Si (poly-Si) channel/gate oxide interface is proposed for macaroni MOSFETs, the unit cell of 3-D NAND Flash memory. The model is derived by considering a cylindrical coordinate system and is expressed as the Lambert W function and the cosine integral. To verify our model, a computer-aided design (TCAD) simulation tool, including a carrier transport model for poly Si channel, is used and calibrated against experimental data of 3-D NAND string current. The validity of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\psi _{\text {B}}$ </tex-math></inline-formula> -model at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {GS}} &gt; {V}_{\text {FB}}$ </tex-math></inline-formula> is demonstrated by comparing the model with simulation data extracted from calibrated exponential density of states (DOS) distribution for grain boundary traps (GBTs). In the verification stage, simulations are also implemented under various exponential DOS distributions and channel hole radius, and a good agreement between the model and the simulation data is achieved.