Modeling dual inlaid feature construction

Abstract

Dual inlaid construction of copper interconnect structures involves a sequence of tightly coupled plasma processes with subtle variations in one process impacting subsequent processes. An integrated plasma reactor/feature physics based modeling suite has been applied to three-dimensional (3D) dual inlaid (DI) feature construction. Specifically, the goal of this article is to understand process interdependencies during DI construction. The DI feature is used in inlaid copper interconnects to define metal lines and their connection to the metal layer below. One advantage of the DI feature is only one metallization step (barrier deposition/seed deposition/electroplating/chemical mechanical polish) is required to deposit metal into both the metal lines and the via connections to the metal layer below. Discussed will be the 3D feature modeling of fluorocarbon plasma etching of vias and trenches in SiO2 to construct dual inlaid features. The model includes 11 steps in the dual inlaid construction process. Papaya, the feature model, applies the many mask, etch, and deposition process steps as characterized by reactor models onto an evolving feature. The model thus allows for an integrated study of the dual inlaid feature construction including the cumulative effect of prior etch steps on subsequent etch steps. Polymer build up can shield a surface from enchants and plays a role in etch selectivity. The amount of polymer in the via and trench etch is shown to affect the amount of bowing in the feature as decreased passivation from less polymer leads to more chemical etching on the via and trench sidewalls. The height of the “slug” used to protect the via in a via first trench last (VFTL) DI integration controls the fencing or notching seen at the via opening. As the slug to dielectric etch ratio is increased the etching at the via opening is enhanced leading to notching at the via opening as well as widened and sloped vias. A larger trench width versus via diameter leads to larger via openings and more flared vias. Also, bilayer resist VFTL and trench first via last (TFVL) DI integration schemes have been modeled. TFVL DI integration is shown not to suffer issues at the via opening (fencing, notching, and flare) as seen in the VFTL DI integration scheme.