Modeling Attack Resistant Strong PUF Exploiting Obfuscated Interconnections With <0.83% Bit-Error Rate

Abstract

Silicon-based physical unclonable functions (PUFs), which exploit the natural random entropy during the chip manufacturing process, can generate random, unique and stable responses upon an input challenge. Instead of using complex crypto-algorithms, strong PUFs having a huge number of challenge-response pairs (CRPs) can be directly employed for low-cost authentication in many emerging IoT applications [1] –[4]. Yet, they typically are vulnerable towards machine learning (ML) attacks and exhibit a high bit-error rate (BER) [1], [5]. Even though the popular PUF obfuscation approach (e.g. hash processing and linear feedback shift register) can significantly enhance the ML attack resistance, they typically require extra processing steps involving PUF responses, which can inevitably degrade the achievable BER. This work reports an obfuscated interconnection physical unclonable function (OIPUF) containing two identical Ol blocks with intertwined stagewise intermediary networks. When compared with the conventional obfuscation approach, we explore the exponential stagewise interconnection to achieve intrinsic obfuscation without requiring extra hardware resources nor sacrificing the PUF reliability. We further propose a metastability-detection arbiter (MD-arbiter) array to improve the PUF reliability, demonstrating a measured worst case BER of 0.83% and an 1162x separation between inter and intra hamming distance (HD) while attaining a ML attack prediction accuracy of $\sim$ 50.59% with up to 10M training CRPs.