Modeling and simulation of printed circuit board drop test

Abstract

Modeling and simulation of drop tests for printed circuit boards (PCB) was conducted for flip chip on board (FCOB) assemblies. The PCB test vehicle has dimensions of 185 mm by 150 mm with 6 large flip chips (8 mm/spl times/8 mm) and 6 small flip chips (3 mm/spl times/3 mm) mounted with underfill encapsulation. The PCB specimen was clamped at two edges on a test fixture and mounted on the drop test machine platform. A drop height of 1.0 m was used for repeated drop tests. In this study, finite element analysis (FEA) of the drop test for the PCB specimen was modeled using the Pam-Crash software. Dynamic modeling and simulation of the drop test sequence of events was established. The modeling approach employs the experimentally measured displacement history (from the high speed camera) at the clamp edges of the PCB as inputs to the local model analysis to compute the displacement and acceleration. The FEA modeling and simulation results show that the predicted displacements and accelerations at selected locations on the PCB agreed satisfactorily with the measured results.