Modeling and Simulation of Negative Capacitance Gate on Ge FETs

Abstract

In this work, a polysilicon-ferroelectric (FE) gate capacitor is proposed to be stacked on the Ge-MOSFET to simultaneously maintain the stability and the potential amplification in the sub-threshold region of a Negative Capacitance Field Effect Transistor (NCFET). Hence, the non-hysteresis ID-VG characteristics with sub-60mV/dec subthreshold slope (SS) can be designed. Based on the simulation results, a small signal capacitance model (Fig.1(b)) which includes the effects of gate-to-source/drain overlap, interface trap states at oxide/Ge, and polysilicon/FE/metal is presented. In the sub-threshold region, the value of -CFE should be as close (but larger) to CMOS as possible to achieve large potential amplification. However, when the strong inversion of the MOS occurs and CMOS increases rapidly, -CFE > CMOS is still required to stabilize the NCFET.[1] The desirable properties can be achieved by utilizing the polysilicon capacitance (Cpoly) which is a function of the applied voltage. The magnitude of the effective CFE’ (=1/(1/CFE + 1/Cpoly)) approaches to CMOS capacitance closely at the subthreshold region and increases when strong inversion of Ge-MOSFET occurs (Fig.2(a)). Hence, a hysteresis-free steep SS NCFET is obtained. The optimized hysteresis-free polysilicon-FE NCFET achieves SS as low as 43mV/dec in the simulation (Fig.2(b)). Its optimized SS is further improved when the direct S/D overlap with floating metal of Ge-MOSFET increases (Fig.2(b)). On the other hand, the trapped charges in the FE interface will compensate the polarization of the ferroelectric material, and thus degrade the negative capacitance. By tuning the FE thickness and adding fixed charges, its effect on CFE can be balanced through our optimization approach. Reference: [1] S. Salahuddin and S. Datta, Nano letters, vol. 8, no. 2, pp. 405–410 (2008). Figure 1