Modeling and simulation of ΣΔ frequency synthesizers

Abstract

This paper describes a very effective approach to model the /spl Sigma//spl Delta/ phase noise and its effect on the closed loop VCO phase noise and spur of /spl Sigma//spl Delta/ frequency synthesizers. The /spl Sigma//spl Delta/ phase noise is caused by the RF divider which performs uneven divisions of the VCO output under the control of a /spl Sigma//spl Delta/ calculator. The /spl Sigma//spl Delta/ phase noise spectrum can be derived in a closed form by Fourier series expansion due to the periodic property of /spl Sigma//spl Delta/ sequences. One way to estimate the closed loop VCO phase noise is to linearly apply the PLL transfer function to the /spl Sigma//spl Delta/ phase noise spectrum. However, when the /spl Sigma//spl Delta/ phase noise is not sufficiently suppressed by the loop filter, a nonlinear estimation has to be used. It was found that the spurs can be created by the nonlinearity of the VCO in conjunction with the /spl Sigma//spl Delta/ phase noise, Nevertheless, the circuit nonlinearity is more dominant than the VCO nonlinearity. A performance comparison between a simulation and bench measurement of a MASH11 based synthesizer IC was performed and an excellent correlation was achieved.