Abstract
A 3mW inherently glitch-free phase-switching prescaler and a loop filter with a 0.2mW capacitance multiplier are proposed for a /spl Sigma//spl Delta/ PLL synthesizer in 0.35/spl mu/m CMOS. The /spl Sigma//spl Delta/ noise folding is minimized by optimal design of /spl Sigma//spl Delta/ modulator and minimized PLL nonlinearities. The synthesizer has a 9.4% tuning range of 2.23-2.45GHz. The phase noise is -90dBc/Hz at 10kHz, and -128dBc/Hz at 10MHz offset.
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