Modeling and analysis of TSV noise coupling and suppression methods for 20nm node and beyond

Abstract

With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper, the noise coupling effect between TSVs and corresponding suppression methods were modeled and analyzed. Effect of variations of structural parameters on noise coupling are investigated and results are explained based on specifications of advanced technology node. In order to alleviate noise effect under fine pitch scenario, different noise suppression methods are discussed and compared. The guard-ring didn't demonstrate much noise reduction over the whole frequency spectrum, with slightly better performance within the low frequency range. The buried oxide layer of SOI technology also showed little suppression effect in blocking substrate noise. However, the TSV array scheme is significantly effective in noise suppression over the whole frequency spectrum.