Model-based optimization of High Level Synthesis directives

Abstract

High Level Synthesis (HLS) tools improve the speed of FPGA hardware design entry compared to traditional hardware description languages by raising the level of design abstraction. Using compiler directives to guide the tool, a wide variety of hardware architectures can be obtained without modification of the original behavioural code. However, selecting an optimal application of directives from this large design space can be daunting and time-consuming for a designer since evaluating a particular setting of directives requires running the FPGA tool flow. This work considers the use of sequential model-based optimization (SMBO) methods for automatically selecting directive settings. These methods construct models of the design space to guide the optimization process and minimize the number of tool evaluations. In this paper, we evaluate the use of SMBO for selecting HLS directives and extend the method to relate multiple uses of the same directive within a design. We observe that SMBO can quickly find optimal directive settings in a space of tens of thousands of possible directive configurations and find that our proposed extension can further improve the convergence rate over the standard method.