Abstract
In this work, a stable and accurate model order reduction method for large-scale partial element equivalent circuit (PEEC) models with many delays is proposed. The method reduces the dimension of the original model by interpolating the original transfer function. The interpolation points are iteratively selected using a greedy algorithm. An efficient error estimator for the reduced transfer function makes the greedy algorithm very successful in both, properly selecting the interpolation points and tightly measuring the error of the reduced transfer function. The resulting reduced-order model is accurate both in the frequency and in the time domain. Numerical tests have shown that the reduced-order model successfully filters the instability behavior of the original model and exhibits stability over a large time interval.
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